A flat panel display device has characteristics of small volume, low power consumption, no radiation etc., and has gradually replaced a bulky CRT (Cathode Ray Tube) display device so as to occupy a dominant position in the display market. A commonly used flat panel display device includes a LCD (Liquid Crystal Display), a PDP (Plasma Display Panel), or an OLED (Organic Light-Emitting Diode) display device.
In the imaging process, each pixel in the LCD or an active matrix OLED (Active Matrix Organic Light-Emitting diode, abbreviated to AMOLED) display device is driven by a thin film transistor (abbreviated to TFT) integrated into the array substrate, so as to realize the image display. The thin film transistor functions as a light control switch, is critical to realize the display of the LCD or the OLED display device, and is directly related to the development of the display device with high performance.
The LCD may be of a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, or an ADSDS (ADvanced Super Dimension Switch) mode, etc. As for the ADSDS mode, the array substrate simultaneously includes a pixel electrode and a common electrode, the electric field generated between edges of slit electrodes in the same plane and the electric field generated between the slit electrode layer and the plate-shaped electrode layer constitute a multidimensional electric field so that all oriented liquid crystal molecules between slit electrodes and directly above the electrodes in the liquid crystal cell are oriented, to improve the operation efficiency of the liquid crystal molecules and increase light transmission efficiency, while increasing the viewing angle.
The thin film transistor mainly includes a gate, a gate insulating layer, an active layer, a source and a drain. FIG. 1 is a sectional view of an array substrate in an ADSDS mode in the prior art. The array substrate is manufactured by five patterning processes (in other words, masking processes) from bottom to top, and the used masks include a mask for the common electrode, a mask for the gate, a mask for the active layer and the source/the drain, a mask for a via in a passivation layer, and a mask for the pixel electrode. In the array substrate, the common electrode and the gate are formed by two patterning processes with a transparent conductive material and a metal material, respectively.
FIG. 2 is a sectional view of an array substrate in another ADSDS mode in the prior art. The array substrate is manufactured by six patterning processes (in other words, masking processes) from bottom to top, and the used masks include a mask for the gate, a mask for the active layer, a mask for the source/the drain, a mask for the pixel electrode, a mask for a via in a passivation layer, and a mask for the common electrode. In the array substrate, the source/the drain and the pixel electrode are formed by two patterning processes with a metal material and a transparent conductive material, respectively.
In the array substrates with the above-mentioned two kinds of structures, the common electrode and the gate, as well as the source/the drain and the pixel electrode are formed by two masking processes, resulting in a complex process and a high cost. Similarly, as for the array substrate in the TN mode, the VA mode and the OLED display device, the same problem also exists.